The present invention relates to a chip-on-chip multichip module in which a plurality of chips are mounted on a chip as a substrate including pad electrodes; the substrate chip included in the module, and the chips mounted on the substrate chip.
Recently, a xe2x80x9csingle-chip system LSIxe2x80x9d, that is, an LSI with a multiplicity of functions integrated together within a single chip, has been introduced and various design techniques have been proposed for the single-chip system LSI. In particular, an advantage of the single-chip system LSI is that a high-performance multifunction device is realized with a multiplicity of functions such as memories of, e.g., a dynamic random access memory (DRAM) and a static random access memory (SRAM) and circuits of, e.g., logic and analog circuits, integrated within a single semiconductor chip. However, in realizing such a system LSI, i.e., in fabricating a device with a multiplicity of functions, the following problems have been encountered.
One of the problems is that, when a system LSI develops to a higher degree, the cost of fabricating a device increases because a greater power is required and production yield decreases due to increase in total chip area.
Another problem is that it is difficult to combine a process for embedding mutually different types of devices such as a DRAM and a flash memory (FLASH) together with a pure CMOS process. This is because it is very difficult for a process performed on a device with a particular function and the pure CMOS process to have the same progress of development. Thus, the development of a process for embedding mutually different types of devices together is lacking a year or 2, behind that of the pure CMOS process using the cutting-edge skills. As a result, the production cannot meet the needs on the market timely.
To solve the problems, a chip-on-chip system LSI using a module including a plurality of chips was proposed in Japanese Laid-Open Publication No. 58-92230. In this chip-on-chip multichip module, pad electrodes formed on the upper surface of a chip as a substrate (i.e., a mother chip) are connected to respective pad electrodes formed on the upper surface of each chip to be mounted (i.e., daughter chip) with bumps. These chips are bonded and electrically connected to each other, thereby making a module including a plurality of chips. Unlike a single-chip system LSI, in the chip-on-chip multichip module, a multiplicity of functions are incorporated into a plurality of chips separately. Thus, it is possible to reduce the scale of each chip, and to increase the yield thereof. In addition, the module can also easily include mutually different types of devices that are also different in process generation. As a result, the resultant device is easily implemented as a multifunction device. Furthermore, in a system LSI that utilizes a chip-on-chip multichip module, each wire length required for communication between the mother and daughter chips is extremely short compared to a technique using other multichip modules. Therefore, high-speed communication can be obtained, and thus realizing communication equal to that between blocks in a known single-chip system LSI.
Thus, the chip-on-chip multichip module is an important technique replacing the known single-chip system LSI, but involves the following problems.
A first problem is that the cost of connecting the chips together increases. In general, to connect chips together, bumps are formed on pad electrodes of each chip, and then daughter chips are bonded onto a mother chip so that the chips are connected to each other. However, if the pad electrodes are different in shape or arrangement between the daughter chips, different photomasks for forming the bumps need to be made individually with respect to different daughter chips and the mounting process needs to be changed with respect to each different daughter chip. As a result, the mounting cost invariably increases.
A second problem is that, in making a module, the sufficient bonding strength between chips cannot be ensured. For example, in connecting the chips to each other, if an insufficient number of pad electrodes are formed or a great number of pad electrodes are biasedly arranged near a particular side of a chip bonding strength between chips is excessively decreased.
A third problem is that an insufficient voltage is applied from the mother chip to the daughter chips. In general, according to the shrinkage of design rules for downsizing an element included in an LSI, a device also has its height decreased. Then, the cross-sectional area of wires decreases and the sheet resistance thereof increases. Accordingly, in fabricating a mother chip by a downsizing process using the cutting-edge skills, a power source line needs to be made thicker than in a process using older skills. As a result, the downsized element involves drawbacks.
A fourth problem is that wiring delay increases when signals are transmitted among daughter chips. In a multichip module where a plurality of daughter chips are bonded onto a mother chip, signals are transmitted between the daughter chips via wiring formed on the mother chip. Thus, impedance matching of signal lines formed on the mother chip greatly affects communication efficiency among the daughter chips. As a result, because of the increases in sheet resistance of the wiring and in wiring capacitance due to the downsizing, signals are transmitted between the daughter chips at a lower speed.
A fifth problem is that it is difficult to ensure flexibility in designing because the relationship between the total chip area of the mother chip and that of daughter chips has limitations. In general, input and output of signals between a multichip module and external devices are performed via the mother chip. Thus, when a plurality of daughter chips are bonded onto the mother chip, the mother chip requires an area for bonding the daughter chips thereto and an area for disposing I/O parts for inputting and outputting signals to the external devices. That is to say, relationship between the total chip area of the mother chip and that of the daughter chips reduces the flexibility in designing a chip-on-chip multichip module.
It is therefore an object of the present invention to provide a high-performance chip-on-chip multichip module, chip as a substrate, and set of chips that are mounted on the chip, with low cost and high flexibility in designing.
Specifically, an inventive set of small semiconductor chips is mounted on a large chip including a plurality of pad electrodes. Each of the small semiconductor chips includes, on its face, a plurality of pad electrodes that are arranged in an array. The pad electrodes of the small semiconductor chips are of a same size and a same shape, arranged at a same pitch, and made of a same material. The pitch is equal to a pitch between the pad electrodes of the large chip.
In the set of small semiconductor chips, the pad electrodes of all the small semiconductor chips are of the same size and shape, arranged at the same pitch, and made of the same material. Thus, the process steps of simultaneously mounting the small semiconductor chips onto the large chip can be easily performed. For example, the same photomask can be used to form bumps during the mounting process steps for making a module. As a result, the small semiconductor chips to be mounted are effective for making a multichip module at a low cost.
In one embodiment of the present invention, each of the small semiconductor chips may further include an internal circuit. Part of the pad electrodes of each of the small semiconductor chips may be electrically connected to the internal circuit. At least one of the pad electrodes, other than the part of the pad electrodes, may be electrically isolated from the internal circuit in each of the small semiconductor chips. Then, the resultant multichip module has a sufficient bonding strength. In addition, since the pad electrodes that require no electrical connection are electrically isolated from the internal circuit in each of the small chips, no electrical error occurs.
In another embodiment, the pad electrodes may be of a same size and arranged at a same pitch so that the size and the pitch is each standardized to take a discrete value. Then, the variety of photomasks used to form bumps during the mounting process steps for making a module can be minimized. As a result, the mounting cost can be further reduced.
In still another embodiment, the set of small semiconductor chips may include at least one element selected from the group consisting of a chip capacitor, a chip resistor, and a chip inductor. In such a case, if the pad electrodes of the chip capacitor, chip resistor, and chip inductor are of the same shape and arranged at the same pitch as the pad electrodes formed in an array on each of the small chips, these components can be mounted in any location on the large chip of a substrate. As a result, it is possible to select components freely and to design the chip more flexibly.
An inventive large semiconductor chip on which a plurality of small chips, each including a plurality of pad electrodes, are mounted. The large semiconductor chip includes, on its face, a plurality of pad electrodes that are arranged in an array. The pad electrodes of the large semiconductor chip are of a same size and a same shape, arranged at a same pitch, and made of a same material. The pitch is equal to a pitch between the pad electrodes of each of the small chips. The large semiconductor chip is a substrate that is used only for forming interconnects and includes no semiconductor element.
In the large semiconductor chip, the pad electrodes of the large semiconductor chip are of the same size and shape and the same material and the pitch between the pad electrodes of the large semiconductor chip is equal to a pitch between the pad electrodes formed on each of the small chips. Thus, the process steps of simultaneously mounting the small chips onto the large chip can be easily performed. Therefore, the large chip is usable for making a multichip module at a low cost. In addition, since the large chip is made of a semiconductor material, this large chip shows the same thermal expansion coefficient as that of the small chips. Thus, a highly reliable multichip module is realized by using this large semiconductor chip as a substrate. Since the large semiconductor chip is a substrate that is used only for forming interconnects therein and includes no semiconductor element, the process steps of fabricating the large semiconductor chip on which the small chips are mounted can be simplified. As a result, the fabricating cost is reduced and the development is accelerated. Further, by using this large semiconductor chip used only for forming interconnects, it is possible to eliminate drawbacks such as deterioration in a power source impedance and increase in wiring delay. Moreover, since the large semiconductor chip of S the substrate includes no semiconductor element such as a transistor, the production yield is expected to be close to 100%. In some cases, testing the substrate chips for shipping can be simplified, thus further reducing the fabricating cost. The absence of a semiconductor element allows the large semiconductor chip of the substrate to be designed so as to have only a minimum area required for making a module. As a result, it is possible to select small chips to be mounted more freely and to design the chips more flexibly. The large semiconductor chip of the substrate used only for forming interconnects does not need to have a microscopic pattern. Thus, it is possible to use an existing semiconductor process of an older generation, thus further reducing the cost of fabricating a substrate chip.
In one embodiment of the present invention, the large semiconductor chip may further include: a ground layer; a power source layer; at least one wiring layer for transmitting signals; a pad electrode layer where the pad electrodes are arranged; and a semiconductor substrate. The ground, power source, wiring, and pad electrode layers may be formed over the semiconductor substrate with an insulating layer each interposed therebetween. The ground layer may be formed over almost the entire surface of the semiconductor substrate. Then, the ground and power source layers have low impedances, thus making a multichip module made up of chips more easily. Also, since the cost of patterning the ground layer is not needed, the cost of fabricating a wiring substrate (i.e., a substrate chip) can be further reduced.
An inventive multichip module includes: a large chip; and a set of small chips mounted on the large chip. Each of the large chip and the small chips includes, on its face, a plurality of pad electrodes that are arranged in an array. The pad electrodes of the large chip are of a same size and a same shape, arranged at a same pitch, and made of a same material. The pad electrodes of the small chips are of a same size and a same shape, arranged at a same pitch, and made of a same material. The pitch is equal to a pitch between the pad electrodes of the large chip.
In the multichip module, as described above, the process step of simultaneously mounting the small chips onto the large chip can be easily carried out to make the module. As a result, the multichip module can be made at a low cost.
In one embodiment of the present invention, each of the small chips may include an internal circuit. Part of the pad electrodes may be electrically connected to the internal circuit in each of the small chips. At least one of the pad electrodes, other than-the part of the pad electrodes, may be electrically isolated from the internal circuit in each of the small chips. Then, a highly reliable multichip module with a sufficient bonding strength is realized.
In another embodiment, the pad electrodes of the large chip and the small chips are preferably of a same size and arranged at a same pitch so that the size and the pitch is each standardized to take a discrete value.
In still another embodiment, the large chip is preferably a substrate that is used only for forming interconnects and includes no semiconductor element.
In yet another embodiment, the large chip preferably further includes: a ground layer; a power source layer; at least one wiring layer for transmitting signals; a pad electrode layer where the pad electrodes are arranged; and a semiconductor substrate. The ground, power source, wiring, and pad electrode layers are preferably formed over the semiconductor substrate with an insulating layer each interposed therebetween. The ground layer is preferably formed over almost the entire surface of the semiconductor substrate.
In still another embodiment, the set of small chips may include at least one element selected from the group consisting of a chip capacitor, a chip resistor, and a chip inductor.